Simulator stats

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Total GPU cycles (incl. kernel-launch latency) Instructions executed (thread-level) Warp instructions issued IPC, instructions per cycle (whole run) Achieved occupancy, percent (last kernel) L1 global reads: accesses L1 global reads: hits L1 global reads: merged into an outstanding miss (MSHR hits) L1 global writes: accesses L1 global writes: hits L2 global reads: accesses L2 global reads: hits L2 global writes: accesses L2 global writes: hits L2 global writes: allocated a new line L2 local-memory writes: hits L2 local-memory writes: misses L2 local-memory writes: sector misses L2 local-memory writes: allocated a new line L2 cross-chiplet reads: accesses L2 cross-chiplet reads: hits L2 bandwidth, GB per second (last kernel) DRAM reads (requests) DRAM writes (requests) Shared-memory bank conflicts L1 bank conflicts Simulator wall time (seconds) Simulation speed (GPU cycles per real second) Simulation speed (instructions per real second) Slowdown vs real silicon (times)