Kiet Vu

I’m a sophomore at Purdue studying Computer Engineering, with a concentration in Semiconductors and Microcontrollers. I love reverse engineering and digging into hardware.

So far I’ve designed a RISC-V CPU from scratch, fixed a GPU simulator, and reverse-engineered a chip from its GDS. More in the Blog.

Right now, I’m dissecting my M4 MacBook’s performance and GPU counters, Dynamic Caching, and TLB, inspired by the reverse-engineering efforts at Asahi Linux.

I’m looking for Summer 2027 internships in RTL design, verification, or GPU/CPU architecture.

Education

• Dean’s List & Semester Honors, Fall 2025 and Spring 2026
• Presentation with Distinction, Spring 2026 Undergraduate Research Conference

Experience

• Leading a team of 3 on the Ethernet RX datapath for a fixed-function GPU on FPGA. I wrote the frame detector, address parser, and CRC-32 in SystemVerilog.
• Defined the host-to-GPU command protocol over raw Ethernet, including the payload formats for register writes and vertex streaming.

• Fixed API failures caused by SSL handshake errors by falling back to curl when Python’s requests library failed.
• Refactored legacy data source modules onto a shared base class and merged 1,800+ historical records into SQLite.

Projects

• Accel-Sim / GPGPU-Sim fixes (GitHub, write-up). Two fixes merged upstream in the GPU simulator. My new L2 write-hit counter raised correlation with real NVIDIA hardware from 0.88 to 0.999 on Rodinia, and a PTX parser fix got PTX mode running again on CUDA 11+.
• Jane Street ASIC Puzzle (GitHub, write-up). Reverse-engineered a chip from its layout back to what it computes, then rebuilt it RTL to GDS. Picked by Jane Street as one of their favorite solutions.
• 5-Stage Pipelined RV32I CPU (GitHub). A RISC-V core written from scratch in SystemVerilog. Passes 100% of the RISCOF compliance suite and goes all the way to a Sky130 layout at 95.2 MHz.
• KV-PIMple (GitHub, write-up). A KV-cache allocator for LLM decode that lines blocks up with HBM rows for processing-in-memory. Row-hit rate goes from 0.77 to 0.96, for 2.3× effective bandwidth on published timing (about 1.6× on AttAcc’s cycle-level PIM simulator).
• Cache Simulator (GitHub). A configurable cache in C++ with 4 write policies, 4 replacement policies, 3C’s miss classification, and design-space sweeps.

Clubs

• Designed PCBs for a rechargeable armor plate, a fluorescent projectile charger, and an audio visualizer.

Toolbox

languages

Verilog / SystemVerilog, C / C++, Python, CUDA, PTX / SASS, Tcl, MATLAB

architecture

GPU architecture, RISC-V, HBM / PIM, Ethernet, AXI, AMBA, FPGA

tools

LibreLane, Yosys, Icarus Verilog, Spike, RISCOF, Accel-Sim / GPGPU-Sim, Ramulator 2, Nsight Compute, Altium, EasyEDA, Linux, Git